By S. Takagi (auth.), Dr. Athanasios Dimoulas, Evgeni Gusev, Professor Paul C. McIntyre, Professor Marc Heyns (eds.)
Will nanoelectronic units proceed to scale in response to Moore’s legislations? At this second, there isn't any effortless solution on account that gate scaling is swiftly rising as a major roadblock for the evolution of CMOS know-how. Channel engineering in response to high-mobility semiconductor fabrics (e.g. strained Si, replacement orientation substrates, Ge or III-V compounds) may well support triumph over the stumbling blocks in view that they provide functionality enhancement. There are a number of matters even though. will we understand how to make complicated engineered substrates (e.g. Germanium-on-Insulator)? that are the easiest interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? do we method those fabrics in brief channel transistors utilizing flows, toolsets and know the way just like that during Si expertise? How do those fabrics and units behave on the nanoscale? The reader gets a transparent view of what has been performed to this point, what's the state of the art and that are the most demanding situations forward sooner than we come any with regards to a achievable Ge and III-V MOS technology.
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Extra info for Advanced Gate Stacks for High-Mobility Semiconductors
Dependence of the eﬀective mobility of electrons and holes in the channel on the Si surface orientation and channel direction  surface by microwave-exited high-density plasma oxidation/nitridation, and very low 1/f noise is realizing by using this oxidation/nitridation technology [8, 16]. In this chapter, we demonstrate that low noise balanced CMOS that is very useful for analog/digital mixed signal circuits can be fabricated on a very smooth Si(110) surface by using a newly developed ﬁve-step room temperature clean and the microwave-excited high-density plasma oxidation process.
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